Conventional computer printers typically utilize laser or ink-jet technology to transfer a raster description of the text and images to be printed into a complete printed page. Such printers make use of printer controllers that normally employ a combination of RISC processors and ASIC devices or ASIC devices having embedded RISC processors. Printer controllers perform the raster image processing required to convert the page description language (PDL) statements and raster files sent to the printer into a form that the printer can act upon.
Typically within the printer controller, the RISC/ASIC devices are employed in a pipeline to perform first the task of interpreting printer control language/post script instructions/data and forming a display list equivalent. Then the second stage performs rendering of data from display lists and converts it to printer specific raster data. These tasks usually require a significant amount of memory within the printer. Such local memory for the printer controller pipeline is usually supplied by way of standard memory modules SIMM/DIMM configured to suit the printer controller application.
FIG. 1 illustrates the steps required to process the input data that a printer typically receives from a conventional personal computer (PC). The output from the PC normally is supplied by a printer driver 101 that prepares an output print file. This file includes a set of instructions and data in printer control language and postscript (x.ps) format. These instructions and data are carried to the printer via standard RS232 or IEEE 1284 cabling and stored in an input buffer memory device 102, typically a first-in-first-out (FIFO) memory. The first computational step in the printer controller pipeline is interpretation 103 of the input Post Script (PS) or printer Control language (PCL) data and form page description language PDL.
Interpretation requiring intensive ‘if-then-else’ processing occurs in the interpretation pipeline stage 103. This process is well suited to the RISC processor. The PDL output from interpretation includes a description of individual elements of graphics data or text data along with the position of these elements on the page. PDL may be in a banded or non-banded format. In banded format discrete bands are defined and formed as a part of the processing and a number of these bands will collectively form, after rendering, a full printer controller output page. In non-banded format, each page is interpreted as a unit and forms, after rendering, an integral part of printer controller output.
The rendering process step 104 reduces the interpreted data to printer specific raster data. The output of the rendering process is a bit map (x.bmp) format in which discrete digitized dots (pixels) are generated to control the output device (e.g. ink-jet pen, laser drum) with proper composite proportions of red, blue, or green. While the format of typical display units is normally in a true R-G-B (red-green-blue) format, the usual format required for typical printer output devices is C-Y-M-K (cyan-yellow-magenta-black), which is a standard chrominance-luminance description format. Pixel data coded in C-Y-M-K can be used to exactly duplicate the three-color information in an R-G-B pixel. The rendering step involves intense multiply-accumulate processing which can be handled by the RISC processor, but is even more suited to a digital signal processors. After rendering, the bit map data is stored in an output buffer memory stage 105 where it is sent as needed to the print head output registers 106.
FIG. 2 illustrates the basic construction of parallel processing and shared memory wherein a main processor device 205 with memory divided into banks 200–203 shares a portion of one or more banks with a parallel digital signal processor 206 which has additional local memory. This architectural arrangement was described by Pawate et al in U.S. Pat. No. 5,678,021 and described further as applied to processor enhanced memory modules PEMM in U.S. patent application Ser. No. 09/058,000. In FIG. 2 the special sections of memory Bank 3 203 are allotted to control register memory space 208 and shared memory 209. This allows the main processor to store configuration data for the co-processor DSP 206 in these special registers and provide all the control signals to drive DSP 206 through a prescribed set of subroutines.